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R1EX25512ASA00A/R1EX25512ATA00A
Data Protect
The protection features of the device are summarized in the following tables. When the Status Register Write Disable
(SRWD) bit of the Status Register is 0 (its initial delivery state), it is possible to write to the Status Register provided
that the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction, regardless
whether write protect ( W ) is driven high or low.
When the Status Register Write Disable (SRWD) bit of the Status Register is set to 1, two cases need to be considered,
depending on the state of write protect ( W ):
? If write protect ( W ) is driven high, it is possible to write to the Status Register provided that the Write Enable
Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction.
? If write protect ( W ) is driven low, it is not possible to write to the Status Register even if the Write Enable Latch
(WEL) bit has previously been set by a Write Enable (WREN) instruction. (Attempts to write to the Status
Register are rejected, and are not accepted for execution). As a consequence, all the data bytes in the memory
area that are software protected (SPM) by the Block Protect (BP1, BP0) bits of the Status Register, are also
hardware protected against data modification.
Regardless of the order of the two events, the Hardware Protected Mode (HPM) can be entered:
? By setting the Status Register Write Disable (SRWD) bit after driving write protect ( W ) low.
? By driving write protect ( W ) low after setting the Status Register Write Disable (SRWD) bit.
The only way to exit the Hardware Protected Mode (HPM) once entered is to pull write protect ( W ) high.
If write protect ( W ) is permanently tied high, the Hardware Protected Mode (HPM) can never be activated, and only the
Software Protected Mode (SPM), using the Block Protect (BP1, BP0) bits of the Status Register, can be used.
Write Protected Block Size
Status register bits
Array addresses protected
0
0
1
1
BP1
0
1
0
1
BP0
Protected blocks
None
Upper quarter
Upper half
Whole memory
R1EX25512A
None
C000h ? FFFFh
8000h ? FFFFh
0000h ? FFFFh
Protection Modes
Write protection of the
Memory protect
W signal
SRWD bit
Mode
status register
Protected area *
1
Unprotected area * 1
1
0
Software
Status register is writable Write protected
Ready to accept Write
protected (SPM) (if the WREN instruction
instructions
0
1
0
1
has set the WEL bit).
The values in the BP1
and BP0 bits can be
changed.
0
1
Hardware
Status register is
Write protected
Ready to accept Write
protected (HPM) hardware write
protected. The values in
the BP1 and BP0 bits
cannot be changed.
instructions
Note:
1. As defined by the values in the Block Protected (BP1, BP0) bits of the Status Register, as shown in the Write
Protected Block Size table.
R10DS0046EJ0200 Rev.2.00
Oct.04, 2010
Page 17 of 20
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